Tech Report CS-91-04
The Lark Project: Design of a Highly Parallel Programmable Logic Array
Scott Apgar, Lloyd Greenwald and Daniel P. Lopresti
In this paper we describe the design and implementation of Lark, a highly parallel programmable logic array. Our goal was to create a chip containing as many simple logic cells as possible, arrayed in a fixed, easy-to-program interconnection scheme. We incorporated as much flexibility and functionality as would fit within these bounds. The $2 mu$ CMOS prototype holds 198 basic cells, each processing two flip-flops and two independent ALU's capable of performing arbitrary boolean functions of up to three inputs. It is currently queued for fabrication by MOSIS. Our estimates indicate that this chip will have a peak performance of 3.7 billion gate evaluations per second.
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