Tech Report CS-89-07

Simulating Switch-Level Networks with Uncertain Transistor Strengths and Node Sizes

Cheryl L. Harkness and Daniel P. Lopresti

February 1989


Numerous techniques for performing switch-level simulation have been developed in recent years. Without exception, these simulators require that the relative conductances, or strengths, of all transistors be precisely specified. We explore the problem of simulating networks with uncertain transistor strength. To solve this problem, we examine the underlying mathematical structure of an existing switch-level simulation algorithm, MOSSIM II, and extend this structure to generate an algorithm for simulating networks with uncertain transistor strengths and node sizes. Such an algorithm may be useful in an integrated design-simulation environment, where designers test circuits while creating them.

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