Tech Report CS-89-32
The B-SYS Programmable Systolic Array
Daniel P. Lopresti and Richard Hughey
We introduce a general architecture for programmable systolic arrays that incorporates the following features: regular topology with nearest-neighbor connections, synchronous SIMD control, interprocessor communication using shared registers, and stream-based I/O. In our model, neighboring processors are granted direct access to one another's working storage: as a result, computation and communication are tightly intertwined, the latter being a natural consequence of the former. We have found that many systolic algorithms can be expressed in such a fashion.
The Brown Systolic Array (B-SYS) is an embodiment of this philosophy. B-SYS is as highly parallel array of simple processing elements tuned for solving combinatorial problems, including sequence comparison. We are currently in the midst of implementing a B-SYS prototype in 2$mu$-CMOS. Although working hardware is not yet available, we have programmed a number of algorithms using B-SIM, a software emulator that has helped us refine the architecture. Preliminary estimates indicate that B-SYS will provide supercomputer performance for the applications of interest.
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