Tech Report CS-89-08
An Architecture for Programmable Systolic Arrays
Richard Hughey and Daniel Lopresti
Systolic algorithms are a systematic and powerful methodology for realizing the potential of very large scale integration. After an initial wave of special-purpose systolic processors, research has turned to the implementation of programmable systolic machines. These machines are often too large and complicated to be able to support massive parallelism: many of the benefits to be reaped from systolic algorithms are lost. Few of the current architectures provide the simple systolic communication of the early special-purpose processors.
The primary contribution of this research is the systolic shared register paradigm. Unlike previous research efforts, the architecture provides a natural means of systolic communication and uses simple processing elements; the architecture can be both easily programmed and easily formed into very large systolic arrays. The main features of the architecture are broadcast instructions, a regular topology, and register sets that are shared between neighboring processing elements. The Brown Systolic Array, an implementation of the concept, is also described. Using the Brown Systolic Array as an example, the programming of these machines is investigated.
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