NER: Exploring the Computational Limits Imposed by Nanotechnologies
Support provided by National Science Foundation
Description
This project has four goals: a) to develop realistic models for chips with nanometer-size dimensions, b) to explore the computational limits that apply under the physical constraints imposed by nanotechnologies, c) to develop architectures and algorithms reflecting these constraints, and d) to incorporate the knowledge acquired in advanced and early graduate instruction. While computational nanotechnologies exist only in the most primitive forms today, we have an opportunity to influence their use akin to that which arose when the VLSI model was developed in the late 1970s. In this model gates are so small that the area of wires is significant. Efficient use of this technology required new algorithms whose efficacy was demonstrated through the development of new complexity-theoretic lower bounds involving chip area and computation time. Our approach will be a) to model technologies such as orthogonal arrays (crossbars) of nanowires and nanotubes and masses of nearly uniform self-assembled elements, b) to extend existing VLSI theory by incorporating the new constraints that emerge, c) to explore new architectures that cope with the complexity-theoretic constraints exhibited by the proposed highly regular architectures and ways of programming them, and d) to devise lectures and/or courses to bring nanocomputation to the attention of students.
Principal Investigator
John E. Savage |
Projects Supported
Details
Amount: | $97,828 |
Dates: | 2002 - 2003 |
Status: | Complete |