R. Iris Bahar
I am a Professor of Computer Science and Engineering at Brown University. I hold a joint appointment in the School of Engineering and Department of Computer Science. My research interests lie broadly in the areas of computer system design and electronic design automation. In particular, my research focuses on energy-efficient and reliable computing, from the system level to device level. Past research topics have included modelling thermal noise effects in nanoscale circuits, design of noise- and error-immune circuits, approximate computing (from systems to circuits), and memory synchronization techniques for multiprocessor systems. Most recently, my research interests have led me to explore applications for near-data processing and design of robust machine learning techniques for robot scene perception.
More information about my research, teaching, and service can be found on my Brown University research page.
Below is a brief overview of a few of my recent research projects.
Concurrent Near-Data Processing Architectures
Recent advances in memory architectures have provoked renewed interest in near-data-processing (NDP) as way to alleviate the “memory wall” problem. An NDP architecture places logic circuits, such as simple processors, in close proximity to memory. This is distinct from processing-in-memory (PIM) where logic computation is effectively integrated into the memory cells/arrays. More ->
Robust and Computationally-Efficient Scene Perception
Technological advancements have led to a proliferation of robots using machine learning systems to assist humans in a wide range of tasks. However, we are still far from accurate, reliable, and resource-efficient operations of these systems. More ->
Modeling of Fundamental Noise Effects in Nanoscale Circuits
Near-threshold and sub-threshold voltage designs have been identified as possible solutions to overcome the limitations introduced by energy consumption in modern VLSI circuits. However, aggressive voltage and gate length scaling will reduce the reliability of logic circuits due to the increasing impact of noise and variability effects. More ->
Managing Microarchitecture Timing Violations with Hardware Transactional Memory
Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the operating frequency or supply voltage prevents timing errors but has a negative impact on performance and energy consumption. More ->