I am a researcher in the VMware Research Group.
My research interests include concurrency and distributed systems.

Previously, I was a PhD student at Brown University, where I worked with Maurice Herlihy and Justin Gottschlich (Intel Labs) on transactional memory and concurrent algorithms for NUMA architectures.

Contact: irina -AT- cs -DOT- brown -DOT- edu


Service

PC: SoCC 2017, PODC 2017, ICDCS 2017, TRANSACT/WTTM 2017, TRANSACT 2016

Reviewer: SPAA 2017, ASPLOS 2017, TPDS, PODC 2016, PPOPP 2015, DISC 2014, PODC 2014, TRANSACT 2014, PACT 2011


Publications

Black-box Concurrent Data Structures for NUMA Architectures
Irina Calciu, Siddhartha Sen, Mahesh Balakrishnan, Marcos K. Aguilera
ASPLOS 2017
[paper] [slides]

NVMOVE: Helping Programmers Move to Byte-Based Persistence
Himanshu Chauhan, Irina Calciu, Vijay Chidambaram, Eric Schkufza, Onur Mutlu, Pratap Subrahmanyam
INFLOW @ OSDI 2016
[paper]

The Adaptive Priority Queue with Elimination and Combining
Irina Calciu, Hammurabi Mendes, Maurice Herlihy
DISC 2014
[paper] [slides]

Invyswell: A Hybrid Transactional Memory for Haswell's Restricted Transactional Memory
Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy
PACT 2014
[paper] [slides]

Improved Single Global Lock Fallback for Best-effort Hardware Transactional Memory
Irina Calciu, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy
TRANSACT 2014, BEST PAPER AWARD
[paper] [slides]

Optimized Single Global Lock Fallback
Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy
WTM 2014

Message Passing or Shared Memory: Evaluating the Delegation Abstraction for Multicores
Irina Calciu, Dave Dice, Tim Harris, Maurice Herlihy, Alex Kogan, Virendra Marathe, and Mark Moir
OPODIS 2013
[paper]

Using Elimination and Delegation to Implement a Scalable NUMA-Friendly Stack
Irina Calciu, Justin Gottschlich, and Maurice Herlihy
HOTPAR 2013 (acceptance rate 46%)
[paper][slides][video]

NUMA-Aware Reader-Writer Locks
Irina Calciu, Dave Dice, Yossi Lev, Victor Luchangco, Virendra J. Marathe, and Nir Shavit
PPOPP 2013 (acceptance rate 18%)
[paper] [slides]

Shared Nothing Transactional Memory
Maurice Herlihy and Irina Calciu
SFMA 2011

Work Experience

Microsoft Research New York City
Research intern, working on concurrent data structures for NUMA machines.
I worked with Siddhartha Sen (MSR) and Marcos K. Aguilera and Mahesh Balakrishnan (VMware Research Group).
New York City, NY, February - May 2015.

Microsoft Research Silicon Valley
Research intern, working on concurrent data structures for NUMA machines.
I worked with Marcos K. Aguilera, Mahesh Balakrishnan, Rama Ramasubramanian, and Siddhartha Sen.
Mountain View, CA, May - August 2014.

Intel Labs
Visiting researcher, working on hybrid transactional memory.
April 2013 - April 2014.

Intel Labs
Research intern, working on hybrid transactional memory.
I worked with Justin E. Gottschlich, Tatiana Shpeisman, and Gilles Pokam.
Santa Clara, CA, June - December 2012.

Oracle Labs
Research intern, working on NUMA-aware algorithms.
I worked with the Scalable Synchronization group.
Burlington, MA, June - September 2011

Google
Software engineer intern in the Platforms Networking team (summer 2010, Mountain View, CA) and Mobile Gateway team (summer 2007, Munich, Germany)

Mozilla
Software engineer intern in the Platform team.
Summer 2009, Mountain View, CA.

Patent Applications Filed

Improving Conflict Detection in Single Global Lock based (SGL) Hybrid Transactional Memory Using Bloom Filters
Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam
2014

Unbounded Hardware Transactional Memory with Forward Progress Guarantees using a Hardware Global Lock
Justin Gottschlich, Irina Calciu, Tatiana Shpeisman, Gilles Pokam
2013

A Software Replayer for Transactional Memory Programs Recorded using a Chunk-based Record and Replay System
Justin Gottschlich, Gilles Pokam, Shiliang Hu, Rolf Kassa, Youfeng Wu, Irina Calciu
2013

Lazy Hardware Lock Elision
Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam
2013

A Hybrid Transactional Memory Algorithm Enabling Hardware and Software Transaction Concurrency
Irina Calciu, Justin Gottschlich, Tatiana Shpeisman
2013

System and Method for Implementing NUMA-Aware Reader-Writer Locks
Irina Calciu, Dave Dice, Victor Luchangco, Virendra Marathe, Nir Shavit, Yossi Lev
2011 (Publication No. US20130290967 A1)

Presentations

The Adaptive Priority Queue with Elimination and Combining, Seminar on Concurrent Computing in the Many-core Era, Dagstuhl, Germany (January 2015)

Abstractions for Scalable Concurrent Data Structures, IBM Programming Languages Day, IBM T.J. Watson, NY (November 2014)

Poster: Software Fallbacks for Haswell Transactional Syncyronization Extensions, New England Networking and Systems Day (NENS), Boston, MA (October 2014)

Poster: Software Fallbacks for Haswell Transactional Syncyronization Extensions, Heidelberg Laureate Forum, Heidelberg, Germany (September 2014)

Poster: Software Fallbacks for Haswell Transactional Syncyronization Extensions, Google I/O Research Day, San Francisco, CA (June 2014)

Poster: Software Fallbacks for Haswell Transactional Syncyronization Extensions, Brown IPP Symposium, Providence, RI (April 2014)

Improved Single Global Lock for Best-effort Hardware Transactional Memory, TRANSACT, Salt Lake City, UT (March 2014)

Poster: mPower: An Access Model for Power Aware Data Structures, Grace Hopper Conference, Minneapolis, MN (October 2013)

Using Delegation and Elimination to Implement a Scalable NUMA-Friendly Stack, HotPar, San Jose (June 2013)

NUMA-Aware Reader-Writer Locks, PPoPP, Shenzhen, China (February 2013)

Hybrid Transactional Memory, Intel Santa Clara, CA (November 2012)

Poster: Hybrid Transactional Memory, Intel Santa Clara, CA (July 2012)

Poster: Hybrid Transactional Memory, Country Fair, Intel Hillsboro, CA (June 2012)

Abstractions for Power-Aware Synchronization in Multicore Architectures, Seminar on Abstractions for scalable multi-core computing, Dagstuhl, Germany (April 2012)

Delegation-based Synchronization, Oracle Burlington, MA (September 2011)

Shared Nothing Transactional Memory, SFMA, Salzburg, Austria (April 2011)

Shared Nothing Transactional Memory, Oracle Burlington, MA (March 2011)

Poster: Network Simulator, Google, Mountain View, CA (August 2010)

Lockfree Data Structures, Mozilla, Mountain View, CA (August 2009)

B.Sc. Thesis: Generic Rapidly Exploring Random Trees, Jacobs University Bremen (June 2009)

Poster: Mobile Gateway Feedback Loop, Google, Zurich, Switzerland (August 2007)