1

 Errors in Crossbars
 John E Savage

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 General Properties of nanoarrays
 NanoFabrics – an early model for nanoarrays
 NanoPLAS – A programmable architecture
 Coping with defects

3

 DeHon (JETC, Vol. 1, No. 2, 2005) predicts one to two orders magnitude
greater density with nanoarrays than FPGAs realized in 22nm lithography,
even if latter components are defectfree!

4

 Axially doped NWs
 Resistance: 0.1MΩ (on) to 10GΩ (off) (>10^{4}
ratio)
 Radially doped NWs
 Use as shield and control spacing or to encode NW.
 Silicide – coating Si with Ni and annealing forms metallic NiSi
 Resistivity of NiSi = 10^{5 }Ωcm, of Si = 10^{3 }Ωcm
 This reduces NW contact resistance to 10KΩ

5

 Chen et al. [2003]:
 Ti/Pt[2] rotaxaneTi/Pt sandwich exhibiting state storage with
resistance change by > x10
 From 500KΩ to 9MΩ for 1600nm^{2} jnctn
 State switched with +/ 2V, read at +/ 0.2V
 Molecular sandwich created with LangmuirBlodgett
 8 x 8 crossbar constructed

6

 SRAMbased programmable crosspoint has area 2,500λ^{2}
versus 25λ^{2} for NW crossing [DeHon 1996].
 NWs can be grown to hundreds of microns in length, but only for large
NWs.
 10μm x 10μm arrays have been demonstrated

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 NWs may break during assembly
 Diameter can be ≈100 atoms
 Statistical nature of contacts
 NWtoMW junctions: small no. of atomic bonds
 E.g. [Huang 2001]: 95% of contacts good
 NWtoNW junctions: composed of 10s of atoms
 E.g. [Chen 2003]: 85% of crosspoints useable
 Statistical nature of doping
 Number of dopants per NW diameter is small

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 NW Defects
 Functional: Good contacts at each end, resistance within range, no
shorts to other NWs
 Defective NWs can be found through testing
 Shells on axial or radial NWs prevent shorts between NWs
 Crosspoint Defects
 Programmable (Most common state)
 Resistance can switched between design limits
 Nonprogrammable (More common than shorts)
 Cannot be turned on – too few molecules at junction
 Shorted into the on state (treat as defective wires)
 Cannot be programmed into the off state

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 [Chen 2003] 8 × 8 crossbar within a 1 μm^{2} area, density
of 6.4 Gbits cm^{2}.^{ }Two 4 × 4 crossbar subarrays
configured to be a nanoscale demultiplexer and multiplexer that were
used to read memory bits in a third subarray. Nanoimprint litho used for
NWs
 [Wu 2005] 34 x34 crossbar memory circuits at 30nm halfpitch
nanoimprint lithography used for NWs, LB for film deposition. Read,
write, erase and crosstalk were also investigated. Also see [Jung 2004]

10

 Heath and Stoddart have implemented a 400x400 array of NWs with density
of 10^{11} bits/centimeter.
 “Modern DRAM circuits have 140nm pitch wires and a memory cell size of
0.0408 mm^{2}.”
 “Here we describe a 160,000bit molecular electronic memory circuit,
fabricated at a density of 10^{11} bits cm^{2} (pitch
33 nm; memory cell size 0.0011 mm^{2}), that is, roughly
analogous to the dimensions of a DRAM circuit projected to be available
by 2020.”

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 NWs in black are drawn high by applied voltages
 Output functions shown
 Programmed crosspoints realize a routing network

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 Goal: turn on one NW in each array dimension
 Earlier lectures describe
 Undifferentiated NW decoders
 Random contact decoder
 Randomized maskbased decoder
 Differentiated NW decoders
 Axially encoded NWs
 Radially encoded NWs

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 WireOR nonrestoring
 Capacitive coupling of input NW to vertical NW
 FET at intersection
 Gives voltage divider
 Inverter shown at right
 Reverse V_{high} and Gnd to obtain buffer

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 Ideal restoration array has one FET/NW
 Stochastic assembly raises its ugly head
 Some NWs may form FETs with multiple vertical NWs
 How many vertical NWs are needed?
 A coupon collector problem

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 Write
 Apply voltage across junction
 Read
 Disconnect one end of each NW
 Drive current from a NW in one dimension to NW in other

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 Crossbars can be used for storage, computation or routing
 Amenable to sparing and remapping
 Challenge:
 Defect tolerance and avoidance

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 PLA with two programmable and restoration/inversion sections
 Address discovery followed by programming
 Twophase clocking will implement sequential logic

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 Signal routing possible in X and Ydirection as well as corner turning.

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 If NWs connected to CMOS wires, lots of time needed for charge
accumulation
 Better solution: use many identically programmed NWs as collective FET
 How does one enter multiple independent inputs?

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 NW sparing
 Both OR output and restoration NWs must work correctly.
 If P_{w} is prob NW is not defective, (P_{w})^{2}
is prob that OR output is useable
 How many NW pairs needed for correct operation?
 NW failure
 P_{c} = prob NW makes good contact on one end
 P_{j} = prob no break in NW of length L_{0}.
 P_{ctrl} = prob NW aligned adequately
 For NW length L = ρ L_{0}, P_{w} = (P_{c})^{2}
x (P_{j})^{ρ} x P_{ctrl}

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 No. nondefective wiredOR NWs
 No. uniquely addressable NWs
 No. nondefective restored NW pairs
 No. uniquely restored terms

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 Goal: reconfigure to route around defects
 E.g. ORterm f = A+B+C+E can be assigned to W3 despite defect

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 This is a matching problem.
 Fig (a) shows defects
 Fig (b): NWs to which OR terms can be mapped
 f_{1} = a+b+c+d, f_{2} = a+c+e, f_{3} = b+c, f_{4}
= d+e
 Fig (c): A matching

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 Our binary model is accurate if each MW provides good control.
 Realistically, some MWs may only partially turn off some NWs.
 Also, some MWs may occasionally fail to control some NWs.
 Our decoders must be faulttolerant!

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 To apply the ideal model to realworld decoders, consider binary
codewords with random errors.
 If c_{ij} = e, the j^{th} MW increases n_{i}‘s
resistance by an unknown amount.
 Consider input A such that the j^{th} MW carries a field. A
functions reliably if a MW for which c_{ik} = 1 carries a field.

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 Consider two errorfree codewords, c_{a} and c_{b}. Let
c_{a}  c_{b}] denote the number of inputs for which c_{a}_{j}
= 1 and c_{b}_{j} = 0.
 The balanced Hamming distance (BHD) between c_{a} and c_{b}
is 2•min(c_{a}  c_{b}], c_{b}  c_{a}]).
 If c_{a} and c_{b} have a BHD of 2d + 2 they can
collectively tolerate up to d errors.

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 In a randomizedcontact decoder, c_{ij} = 1 with some fixed
probability, p.
 If each pair of codeword has a BHD of at least 2d + 2, the decoder can
tolerate d errors per pair.
 This holds with probability > 1 f
when
